A recently introduced merged memory logic (MML) is a device in which a memory cell array part such as a dynamic random access memory (DRAM) and an analog or a peripheral circuit are integrated in one chip. The introduction of the MML results in improving multimedia functions and effectively approaching high integration and speed in semiconductor devices. However, in an analog circuit which is required for high speed, it is regarded as of major importance to develop a semiconductor device having capacitors of large quantity. Generally, in the case that the capacitor has a polysilicon/insulator/polysilicon (PIP) structure, since upper and lower electrodes are formed of polysilicon, oxidation occurs at an interface between the dielectric layer and the upper/lower electrodes, and an oxide layer is formed at the interface. This results in decreasing the total capacitance. Also, a depletion layer formed at the polysilicon layer decreases the capacitance. Thus, the PIP structure is not proper for a device required for high speed and frequency. In order to solve this problem, the structure of the capacitor has been changed to a metal/insulator/silicon (MIS) structure or MIM structure. Having low resistance and no parasitic capacitance due to depletion, the MIM-type capacitor is usually used for high-performance semiconductor devices. Recently, with low resistance, copper is introduced for metal interconnections in the semiconductor device. Also, various capacitors having MIM structures with Cu electrodes are suggested. A capacitor with the MIM structure and a method of forming the same are disclosed in the U.S. Pat. No. 6,025,226 entitled: “Method of forming a capacitor and a capacitor formed using the method” by Gambino et al. A method of simultaneously forming interconnects and capacitors is disclosed in the U.S. Pat. No. 6,081,021 entitled: “Conductor-Insulator-Conductor structure.”
FIGS. 1 through 4 illustrate process cross-sectional views showing a method of a conventional semiconductor device with a capacitor of the MIM structure.
Referring to FIG. 1, an interconnection layer 15 and a lower electrode 10 are formed at a desired region of a semiconductor substrate 5. Conventionally, the interconnection layer 15 and the lower electrode 10 are formed on an insulation layer using a damascene process. An interlayer dielectric layer 7 is formed at the entire surface of the semiconductor substrate 5 having the interconnection layer 15 and the lower electrode 10. The interlayer dielectric layer 7 is patterned to form first and second openings 30 and 20 exposing desired regions of the interconnection layer 15 and the lower electrode 10, respectively. A dielectric layer 22 is conformally formed at the entire surface of the interlayer dielectric layer 7. The dielectric layer 22 covers the inner walls of the first and second openings 30 and 20, and the interconnection layer 15 and the lower electrode 10 which are exposed in the first and second openings 30 and 20, respectively.
Referring to FIG. 2, the upper part of the interlayer dielectric layer 7 is etched to form a trench 32 at the upper part thereof. The trench 32 is formed using a photo lithography process. At this time, the dielectric layer 22 in the first opening 30 is anisotropically etched to expose the interconnection layer 15 therein.
Referring to FIG. 3, the first opening 30, the trench 32, and the second opening 20 are filled with a metal layer to form an interconnection plug 26 connected to the interconnection layer 15 and an upper electrode 24 in the second opening 20. Conventionally, the interconnection plug 25 and the upper electrode 24 can be formed by polishing the metal layer filling the first opening 30, the second opening 20 and the trench 32, by a CMP process. At this time, according to the conventional technology, a native oxide layer can be formed at an exposed surface of the interconnection layer 15 in the first opening 30 during the delay time between forming the first opening 30 and filling it with the metal layer. The native oxide layer on the surface of the interconnection layer 15 increases parasitic resistance and parasitic capacitance to result in decreasing properties of the semiconductor device which is required for high speed and superior frequency. Thus, in order to decrease the contact resistance between the interconnection layer 15 and the interconnection plug 26, an etch process for removing the native oxide is required before filling with the metal layer. During this etch process, the dielectric layer 22 in the second opening 20 can be exposed and damaged.
A mold layer 9 is formed at the entire surface of the semiconductor substrate at which the interconnect 26 and the upper electrode 24 are formed. The mold layer 9 is patterned to form third openings 40 exposing the upper electrode 24 and a desired region of the interconnection plug 26.
Referring to FIG. 4, a metal interconnection 42 is formed to fill in the third openings 40 and to selectively contact to the interconnection plug 26 and the upper electrode 24. The lower electrode 10, the upper electrode 24, and the dielectric layer interposed therebetween compose a capacitor of a semiconductor device.
According the described conventional technology, since the upper electrode 24 has a vertical structure, the area of dielectric layer 22 interposed between the interlayer dielectric layer 7 and the upper electrode 24 is so large as to increase the parasitic capacitance.